1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a selecting device for selecting memory cells in a dynamic RAM (hereinafter referred to as a DRAM) with a multi-bit input/output configuration.
With recent advances in a fine-structure manufacturing process for large-capacity semiconductor memory devices, it is desired to improve the reliability of the process and the manufactured semiconductor memory devices. To improve the reliability of the semiconductor memory devices themselves, an ECC (Error Correcting Circuit) is used in the system. In general, the Error Correcting Circuit is adapted to detect and correct one-bit error. With the errors correcting circuit used in a semiconductor memory devices with multi-bit input/output configurations, if a plurality of bits should fail, errors are not detected and corrected.
2. Description of the Related Art
FIGS. 1a and 1b illustrate a first example of a semiconductor memory device with a multi-bit input/output configuration.
This memory device includes four memory cell arrays MA0, MA1, MA2, and MA3 and a 8-bit input/output configuration. Each memory cell array, for example, memory cell array MA0, has word lines WL00 to WL0j and bit lines BL00 to BL0m wired in a matrix. A transfer transistor TT and a memory cell (CEL00 to CEL0m) are connected at each word-line/bit-line intersection. Each word line WL00 to WL0j is selected by a row decoder DX0 and driven by a row driver DRX0. An address signal supplied to respective column decoders DY0 and DY1 designates the same address and respective row decoders also designate the same address.
The bit lines are connected to corresponding sense amplifiers SA00, SA01, and so on, in pairs. The sense amplifiers sense and amplify signal variations in the memory cells CEL00 to CEL0m. Output signals of sense amplifier SA00 are read onto a data bus BUS via a transfer gate TG and two bits are latched by data latches DL0 and DL1.
Transfer gates TG0 and TG1 are turned ON or OFF by column driver DRY0 and column decoder DY0 through a column selecting line CL00. This allows bit lines BL00, BL01, BL10 and BL11 to be selected.
Other memory cell arrays MA1, MA2 and MA3 have the same configuration as cell array MA0, described above. Note that column decoder DY0 is shared between memory cell arrays MA0 and MA1 and column decoder DY1 is shared between memory cell arrays MA2 and MA3.
Next, the read operation for stored data will be briefly described.
In reading stored data, two bits are read from an array of sense amplifiers SA for each of the memory cell arrays MA0 to MA3 and data of 8 bits in total are read for application to data latches DL0 to DL7 via data bus BUS. At this point, if a column selecting line CL for any given one of sense amplifiers SA should fail, two bits of 8-bit output data will fail. Detection and correction of two bits cannot be made in the system, making use of the ECC impossible.
Recent advances in wiring techniques and manufacturing processes have given rise to metal-layer interconnected semiconductor memory devices. An example of the metal-layer interconnected semiconductor devices is illustrated in FIGS. 2a and 2b. In FIGS. 2a and 2b, like reference characters are used to designate parts corresponding to those in FIG. 1 and description thereof are omitted.
This semiconductor memory device has eight memory cell arrays arranged in one direction (in the column direction in the Figure) and column select lines CL extended on metal second layers on a substrate board (not shown) to pass across columns of sense amplifiers SA so as to share column select lines CL among the columns of sense amplifiers SA (hence memory cell arrays MA0 to MA7).
Row decoders DX0 to DX7 and row drivers DRX0 to DRX7 are provided for memory cell arrays MA0 to MA7, respectively.
DRs are drivers for driving transfer gates TG which select either of paired memory cell arrays MA0 and MA1; MA2 and MA3; . . . ; MA6 and MA7 for connection to corresponding sense amplifiers SA.
In this way, because of multilayer interconnection in which column select lines are formed of metal second layers, one column decoder DY for memory cell arrays MA0 to MA7 allows memory cells CEL to be selected and sense amplifiers SA can share column select lines CL, thus permitting high-density integration.
In reading data, one bit is read from each array of sense amplifiers SA and then latched by the corresponding data latch (DL0 to DL3) so that data of 4 bits in total are output through a data bus.
In the above semiconductor memory device, if column select lines CL belonging to any given array of sense amplifiers SA should fail, 4 bits of output data will all fail. Thus, this semiconductor memory device also cannot use the Error Correcting Circuits, as is the case with the semiconductor memory device of FIG. 1.
As in the semiconductor memory devices of FIGS. 1 and 2, in a semiconductor memory device in which a plurality of bit lines associated with a selected word line through memory cells are activated simultaneously by a common column select line in each memory cell array, if the column select line should fail, many bits will fail simultaneously. Thus, the one-bit-accommodating Error Correcting Circuit cannot be adapted to such a memory device.